1. Field of the Invention
The present invention relates to a test circuit for a differential input circuit, and a test method for a differential input circuit.
2. Description of Related Art
To achieve the increases in operational speed and stability (to ensure an operational margin) in a semiconductor device, a differential input circuit 10 is utilized in which an output is determined by a difference between two input voltages (input differential voltage) or a difference between two input currents (input differential current). FIG. 1 is a diagram illustrating a symbol of the differential input circuit 10. The differential input circuit 10 outputs an output signal OUT corresponding to a potential difference or a current difference between a noninverting input signal INT and an inverting input signal INB that are in a complementary (reverse phase) relationship with each other. In the following, when the noninverting input signal INT and the inverting input signal INB are collectively referred, they are referred to as differential input signals INT and INB.
FIGS. 2 and 3 are circuit configuration diagrams respectively illustrating examples of the differential input circuit 10. FIG. 2 illustrates an example of a voltage comparator circuit 11 that outputs an output signal OUT corresponding to an input differential voltage. FIG. 3 illustrates an example of a current comparator circuit 12 that outputs an output signal OUT corresponding to an input differential current.
Referring to FIG. 2, the voltage comparator circuit 11 is a general differential amplifier circuit having an N-channel input stage. Specifically, the voltage comparator circuit 11 includes: N-channel MOS transistors N1 and N2 that form the input stage; P-channel MOS transistors P1 and P2 that form an active load; and an N-channel MOS transistor N3 that forms a current source. The P-channel MOS transistors and the N-channel MOS transistors are hereinafter respectively referred to as PMOS transistors and NMOS transistors. The NMOS transistor N3 supplies to sources of the NMOS transistors N1 and N2 a current corresponding to a bias voltage Vb supplied to a gate thereof. Differential input signals INB and INT are respectively inputted to gates of the NMOS transistors N1 and N2. The output signal OUT is outputted from a drain connected in common with the PMOS transistor P1 and the NMOS transistor N2.
Referring to FIG. 3, the current comparator circuit 12 includes: PMOS transistors P3 and P4 that form a first current mirror inputted with an input signal INT; an NMOS transistor N4 connected to a drain of the PMOS transistor P4 at a drain thereof; PMOS transistors P5 and P6 that form a second current mirror inputted with an input signal INB; and an NMOS transistor N5 connected to a drain of the PMOS transistor P5 at a drain thereof. The noninverting input signal INT is inputted to the PMOS transistor P3, and the inverting input signal INB is inputted to the PMOS transistor P6. The output signal OUT is outputted from a drain connected in common with the PMOS transistor P4 and the NMOS transistor N4.
Referring to FIGS. 4 to 6, input/output characteristics of the differential input circuit 10 are described. FIG. 4 is a diagram illustrating the input/output characteristics for the case where the normal differential input signals INT and INB are inputted to the normal voltage comparator circuit 11. FIG. 5 is a diagram illustrating the input/output characteristics that takes into account an input voltage offset in the voltage comparator circuit 11. FIG. 6 is a diagram illustrating the input/output characteristics that takes into account an input current offset in the current comparator circuit 12.
Referring to FIGS. 4 and 5, the input/output characteristics of the voltage comparator circuit 11 are described in the case where the differential input signals INT and INB having normal signal levels are inputted. The description below is provided on the assumption that an absolute value of a difference in voltage between the noninverting input signal INT and the inverting input signal INB is defined as an input differential voltage Vd1. Referring to FIG. 4, the voltage comparator circuit 11 outputs a high level output signal OUT when a voltage level of the noninverting input signal INT is higher than that of the inverting input signal INB, and the input differential voltage is Vd1 (time T1 to T2). Also, the voltage comparator circuit 11 outputs a low level output signal OUT when the voltage level of the noninverting input signal INT is lower than that of the inverting input signal INB, and the input differential voltage is Vd1 (before the time T1 and after the time T2).
In general, in the differential input circuit 10, an input offset due to a variation in element or the like may occur. For example, in the voltage comparator circuit 11, an input voltage offset Voff in the range of ±Voff occurs. Given that the absolute value of the input voltage offset is denoted by Voff, an effective input differential voltage in the voltage comparator circuit 11 takes a value (Vd1−Voff) obtained by subtracting the input voltage offset Voff from the input differential voltage Vd1. For this reason, the voltage comparator circuit 11 in which the input voltage offset Voff occurs determines a signal level (voltage) of the output signal OUT based on the effective input differential voltage (Vd1−Voff).
Specifically, the voltage comparator circuit 11 outputs the high level output signal OUT when the voltage level of the noninverting input signal INT is higher than that of the inverting input signal INB, and the effective input differential voltage is (Vd1−Voff), and outputs the low level output signal OUT when the voltage level of the noninverting input signal INT is lower than that of the inverting input signal INB, and the effective input differential voltage is (Vd1−Voff).
Similarly in the current comparator circuit 12, an input current offset Ioff in the range of ±Ioff as illustrated in FIG. 6 occurs due to a variation in element or the like. In this case, an effective input differential current in the current comparator circuit 12 takes a value (Id1−Ioff) obtained by subtracting the input current offset Ioff from an input differential current Id1. Note that we here define an absolute value of a current difference (INT−INB) between the noninverting input signal INT and the inverting input signal INB as the input differential current Id1, and an absolute value of the input current offset as Ioff. The current comparator circuit 12 outputs a high level output signal OUT when a current level of the noninverting input signal INT is higher than that of the inverting input signal INB, and the effective input differential current is (Id1−Ioff), and outputs a low level output signal OUT when the current level of the noninverting input signal INT is lower than that of the inverting input signal INB, and the effective input differential current is (Vd1−Voff).
The differential input circuit as described above is, for example, as described in Japanese Patent Publication No. Heisei 01-263997A1, preferably used as an amplifier that drives a bit line pair connected to a memory (Patent document 1). In a differential amplifier described in Patent document 1, one of differential inputs is pulled up by a memory cell in a non-writing state, and then data is read from the other one of the differential inputs. As described, the one of the differential inputs is pulled up, and therefore a criterion for level comparison of a potential of the data upon verification is strict.
We have now discovered the following facts. In the case of occurrence of the input voltage offset Voff, even if the input differential voltage Vd1 between the differential input signals INT and INB has a normal value, the effective input differential voltage is decreased to (Vd1−Voff), and therefore an operational margin of the voltage comparator circuit 11 is decreased, resulting in instability. Specifically, if the effective input differential voltage is positive (Vd1−Voff>0), the effective signal levels of the differential input signals determining the signal level of the output signal OUT are not inverted. In this case, the output signal OUT exhibits a same signal level as that for the case of absence of the input voltage offset Voff. On the other hand, if the effective input differential voltage is negative (Vd1−Voff<0), the effective signal levels of the differential input signals determining the signal level of the output signal OUT are inverted. In this case, the output signal OUT transits to a level corresponding to the inverted signal level for the case of absence of the input voltage offset Voff. For example, the high-level output signal OUT should have been outputted based on the inputted differential input signals INT and INB; however, if the input voltage offset Voff is larger than the input differential voltage Vd1, the voltage comparator circuit 11 outputs the inverted low level output signal OUT.
Also, if there is no disturbance such as noise to the differential input signals INT and INB, the voltage comparator circuit 11 exhibits the input/output characteristics as illustrated in FIG. 4, whereas if there is the disturbance such as noise, the input differential voltage between the differential input signals INT and INB will be (Vd1−Vn) (Vn is an absolute value of noise voltage) as illustrated in FIG. 7. At this time, the effective input differential voltage taking into account the input voltage offset Voff is (Vd1−Vn−Voff).
Referring to FIGS. 7 to 10, the input/output characteristics are described in the case where noise or the like is mixed into the differential input circuit 10. The description is provided as an example using the voltage comparator 11 as the differential input circuit 10. FIG. 7 is a diagram illustrating the input/output characteristics of the normal differential input circuit 10 that outputs an expected value even if noise having an allowable level is mixed. FIG. 8 is a diagram illustrating the input/output characteristics of the differential input circuit 10 that outputs a signal different from the expected value if the noise having the allowable level is mixed.
As illustrated in FIGS. 7 and 8, during a time period (time T1 to T2) in which the high-level output signal OUT is outputted, in the case where the noise is inputted to the inverting input signal INB, an input differential voltage at a position of occurrence of the noise will be (Vd1−Vn). At this time, the effective input differential voltage is (Vd1−Vn−Voff). In the case where there occurs no input voltage offset Voff, or if the input voltage offset Voff is smaller than (Vd−Vn) as illustrated in FIG. 7, (Vd1−Vn−Voff)>0, and therefore the output signal OUT keeps the normal value (high-level in this case).
On the other hand, referring to FIG. 8, even in the case where the noise has the same level (Vn) as that described above, if the input voltage offset Voff is larger than (Vd1−Vn), the effective input differential voltage will fall below 0. That is, (Vd1−Vn−Voff)<0, and the signal level (high level) of the output signal OUT is inverted down to a low level. As described, the differential input circuit 10 in which the input offset occurs is an unstable circuit that has a small operational margin and is susceptible to noise.
Also, due to a malfunction or the like of a circuit that generates the differential input signals INT and INB, the input differential voltage Vd1 may be decreased. FIG. 9 is a diagram illustrating the input/output characteristics of the normal differential input circuit for the case where the differential input signals exhibiting abnormal values within an allowable range are inputted. Referring to FIG. 9, the effective input differential voltage (Vd1−Voff) of the voltage comparator circuit 11 in which the input voltage offset Voff occurs is further decreased. For this reason, as compared with the case where the normal differential input signals INT and INB are inputted, the voltage comparator circuit 11 is brought into a further operationally unstable state. However, if (Vd1−Voff)>0, the output signal OUT having the normal value (high level in this case) is outputted.
On the other hand, as illustrated in FIG. 10, if the input differential voltage Vd1 is small, the noise voltage Vn may exceed the input differential voltage Vd1. FIG. 10 is a diagram illustrating the input/output characteristics of the differential input circuit that outputs a signal different from the expected value upon input of the differential input signals exhibiting the abnormal values within the allowable range. Referring to FIG. 10, for example, if the noise is mixed into an inverting signal INB, the effective differential voltage (Vd1−Vn) will fall to or below 0. That is, the voltage levels of the noninverting signal INT and the inverting signal INB are inverted, and therefore the output signal OUT is inverted from the high level to the low level. As described, if the input differential voltage Vd1 between the differential input signals INT and INB is small, the differential input circuit 10 will be an unstable circuit that has a small operational margin and is susceptible to noise.
An input/output characteristics test of the differential input circuit 10 is performed under a noise-free environment. For this reason, even in the case of performing the test of the differential input circuit in which the input offset occurs, if the input differential voltage Vd1 between the differential input signals INT and INB is larger than the input voltage offset Voff, the differential input circuit will not be detected as a defective circuit. However, in an actual operating environment, a disturbance due to noise, variation in differential input signal, or the like occurs, and therefore a circuit having a small operational margin often gives rise to a malfunction. Therefore, there are required a test circuit and a test method that can detect a differential input circuit having a small margin, which is likely to malfunction due to an input offset.